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INTEGRATED CIRCUITS
SA8027 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
Product data Supersedes data of 2001 Jul 18 2001 Aug 21
Philips Semiconductors
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
GENERAL DESCRIPTION
The SA8027 BICMOS device integrates programmable dividers, charge pumps and phase comparators to implement phase-locked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable main, auxiliary and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. The main divider is a fractional-N divider with programmable integer ratios from 512 to 65535. Separate power and ground pins are provided to the charge pumps and digital circuits. The ground pins should be externally connected to prevent large currents from flowing across the die and causing damage. VDDCP must be equal to or greater than VDD. The charge pump current (gain) is fully programmable, while ISET is set by an external resistance at the RSET pin (refer to section 1.5, Main Output Charge Pumps and Fractional Compensation Currents). The phase/frequency detector charge pump outputs allow for implementing a passive loop filter.
LOCK TEST VDD GND RFin+ RFin- GNDCP PHP PHI 1 2 3 4 5 6 7 8 9
20 PON 19 STROBE 18 DATA 17 CLOCK 16 REFin+ 15 REFin- 14 RSET 13 VDDCP 12 AUXin 11 PHA
GNDCP 10
SR01649
Figure 1. TSSOP20 Pin Configuration
STROBE 20
LOCK
TEST
PHP
PHI
PHA
APPLICATIONS * 500 to 2500 MHz wireless equipment * Cellular phones (all standards) * WLAN * Portable battery-powered radio equipment. QUICK REFERENCE DATA
SYMBOL VDD VDDCP IDDCP+IDD IDDCP+IDD fVCO fAUX fREF fPC Tamb PARAMETER Supply voltage Analog supply voltage Supply current Total supply current in power-down mode Input frequency Input frequency Crystal reference input frequency Maximum phase comparator frequency Operating ambient temperature VDDCP w VDD Main and Aux. on CONDITIONS
GND CP
AUXin
N/C
FEATURES * Low phase noise * Low power * Fully programmable main and auxiliary dividers * Programmable Normal & Integral charge pumps outputs * Fast Locking Adaptive mode design * Internal fractional spurious compensation * Hardware and software power down * Split supply for VDD and VDDCP * Loop filter bandwidth programmability
VDDPre GND GNDPre RFin+ RFin- GNDCP
1 2 3 4 5 6 7
24
V DD
23
22
21
19 18 17 CLOCK REFin+ REFin- RSET VDDCP N/C
TOP VIEW
16 15 14
8
9
10
11
12
13
DATA
PON
SR02176
Figure 2. HBCC24 Pin configuration
MIN. 2.7 2.7 - - 500 100 5 - -40
TYP. - - 7.7 1 - - - -
MAX. 3.6 3.6 - - 2500 550 40 4 +85
UNIT V V mA A MHz MHz MHz MHz C
ORDERING INFORMATION
TYPE NUMBER SA8027DH SA8027W PACKAGE NAME TSSOP20 HBCC24 DESCRIPTION Plastic thin shrink small outline package; 20 leads; body width 4.4 mm Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (Note 1) VERSION SOT360-1 SOT564-1
NOTE: 1. The SA8027W will be released for production Q2, 2001. 2001 Aug 21 2 853-2244 26947
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
VDD 3 17 CLOCK DATA 18 2-BIT SHIFT REGISTER 22-BIT SHIFT REGISTER PUMP CURRENT SETTING PUMP BIAS
VDDCP 13
STROBE
19
ADDRESS DECODER
CONTROL LATCH
14
RSET
LOAD SIGNALS LATCH 5 RF/MAINin+ RF/MAINin- 6 MAIN DIVIDER FRAC COMP PHASE DETECTOR 8 PHP
AMP SM LATCH 16 REFin+ REFin- 15 SA LOCK SELECT 1 LOCK REFERENCE DIVIDER 2 2 22 9 PHI
LATCH IF/AUXin 12 AUX DIVIDER AMP TEST 2 4 GND
PHASE DETECTOR
11
PHA
20 7, 10 GNDCP
PON
SR02357
Figure 3. Block Diagram (TSSOP20)
TSSOP20 PIN DESCRIPTION
SYMBOL LOCK TEST VDD GND RFin+ RFin- GNDCP PHP PHI GNDCP PIN 1 2 3 4 5 6 7 8 9 10 DESCRIPTION Lock detect output Test (should be either grounded or connected to VDD) Digital supply Digital ground RF input to main divider RF input to main divider Charge pump ground Main normal charge pump Main integral charge pump Charge pump ground SYMBOL PHA AUXin VDDCP RSET REFin- REFin+ CLOCK DATA STROBE PON PIN 11 12 13 14 15 16 17 18 19 20 DESCRIPTION Auxiliary charge pump output Input to auxiliary divider Charge pump supply voltage External resistor from this pin to ground sets the charge pump current Reference input Reference input Programming bus clock input Programming bus data input Programming bus enable input Power down control
2001 Aug 21
3
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
VDD 24 18 CLOCK DATA 19 2-BIT SHIFT REGISTER 22-BIT SHIFT REGISTER PUMP CURRENT SETTING PUMP BIAS
VDDpre 1
VDDCP 14
STROBE
20
ADDRESS DECODER
CONTROL LATCH
15
RSET
LOAD SIGNALS LATCH 4 RF/MAINin+ RF/MAINin- 5 MAIN DIVIDER FRAC COMP PHASE DETECTOR 7 PHP
AMP SM LATCH 17 REFin+ REFin- 16 SA LOCK SELECT 22 LOCK REFERENCE DIVIDER 2 2 22 8 PHI
LATCH IF/AUXin 11 AUX DIVIDER AMP TEST 23 2 GND 3 GNDpre
PHASE DETECTOR
10
PHA
21 6, 9 GNDCP
PON
SR02358
Figure 4. Block Diagram (HBCC24)
HBCC24 PIN DESCRIPTION
SYMBOL VDDPre GND GNDPre RFin+ RFin- GNDCP PHP PHI GNDCP PHA AUXin N/C N/C PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION Prescaler supply voltage Digital ground Prescaler ground RF input to main divider RF input to main divider Charge pump ground Main normal charge pump Main integral charge pump Charge pump ground Auxiliary charge pump output Input to auxiliary divider Not connected Not connected REFin- REFin+ CLOCK DATA STROBE PON LOCK TEST VDD 16 17 18 19 20 21 22 23 24 SYMBOL VDDCP RSET PIN 14 15 DESCRIPTION Charge pump supply voltage External resistor from this pin to ground sets the charge pump current Reference input Reference input Programming bus clock input Programming bus data input Programming bus enable input Power down control Lock detect output Test (should be either grounded or connected to VDD) Digital supply
2001 Aug 21
4
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
Limiting values
SYMBOL VDD VDDCP (VDDCP-VDD) Vin VGND Tstg Tamb Tj Digital supply voltage Analog supply voltage Difference in voltage between VDDCP and VDD (VDDCP VDD) All input pins Difference in voltage between GNDCP and GND (these pins should be connected together) Storage temperature Operating ambient temperature Maximum junction temperature PARAMETER -0.3 -0.3 -0.3 -0.3 -0.3 -55 -40 MIN. +3.6 +3.6 +0.9 VDD + 0.3 +0.3 +125 +85 150 MAX. V V V V V C C C UNIT
Thermal characteristics
SYMBOL Rth j-a PARAMETER Thermal resistance from junction to ambient in free air VALUE 135 UNIT K/W
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
CHARACTERISTICS
VDDCP = VDD = +3.0 V, Tamb = +25 C; unless otherwise specified. SYMBOL Supply VDD VDDCP ITotal IStandby Digital supply voltage Analog supply voltage Synthesizer operational supply current Total supply current in power-down mode VDDCP w VDD VDD = +3.0 V (with main and aux on) logic levels 0 or VDD 2.7 2.7 - - - - 7.7 1 3.6 3.6 - - V V mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
RFin main divider input fVCO VRFin VCO input frequency AC-coupled input signal level Rin (external) = Rs = 50 ; single-ended drive; g max. limit is indicative @ 500 to 2500 MHz fVCO = 2.4 GHz fVCO = 2.4 GHz 500 -18 80 - - 512 indicative, not tested - - - - 300 1 - - 2500 0 632 - - 65535 4 MHz MHz dBm mVPP pF
ZRFin CRFin Nmain fPCmax
Input impedance (real part) Typical pin input capacitance Main divider ratio Maximum loop comparison frequency
AUX divider input fAUXin VAUXin ZAUXin CAUXin NAUX Input frequency range AC-coupled AC coupled input signal level Input impedance (real part) Typical pin input capacitance Auxiliary division ratio Rin (external) = RS = 50 ; ( ) max. limit is indicative fVCO = 500 MHz fVCO = 500 MHz 100 -15 112 - - 128 - - - 3.9 0.5 - 550 0 632 - - 16383 MHz dBm mVPP k pF
Reference divider input fREFin VREFin ZREFin CREFin RREF Input frequency range from TCXO AC-coupled input signal level Input impedance (real part) Typical pin input capacitance Reference division ratio single-ended drive; max. limit is indicative fREF = 20 MHz fREF = 20 MHz SA = SM = "000" 5 360 - - 4 - - 10 1 - 40 1300 - - 1023 MHz mVPP k pF
Charge pump current setting resistor input RSET VSET External resistor from pin to ground Regulated voltage at pin RSET = 7.5 k 6 - 7.5 1.22 15 - k V
Charge pump outputs; RSET = 7.5 k ICP IMATCH IZOUT ILPH VPH Charge pump current ratio to ISET1 Sink-to-source current matching Output current variation versus VPH Charge pump off leakage current Charge pump voltage compliance
2
Current gain = IPH/ISET VPH = 1/2 VDDCP VPH in compliance range VPH = 1/2 VDDCP
-15 -10 -10 -10 0.6 -
+15 +10 +10 +10 VDDCP-0.7
% % % nA V
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
CHARACTERISTICS (continued)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Phase noise (condition RSET = 7.5 k, CP = 00) Synthesizer's contribution to close-in phase noise of 900 MHz RF signal at 1 kHz offset. Synthesizer's contribution to close-in phase noise of 1800 MHz RF signal at 1 kHz offset. Synthesizer's contribution to close-in phase noise of 800 MHz RF signal at 1 kHz offset. Synthesizer's contribution to close-in phase noise of 2100 MHz RF signal at 1 kHz offset. Interface logic input signal levels VIH VIL ILEAK HIGH level input voltage LOW level input voltage Input leakage current logic 1 or logic 0 0.7*VDD -0.3 -0.5 - - - VDD+0.3 0.3*VDD +0.5 V V A GSM fREF = 13MHz, TCXO, fCOMP = 1MHz indicative, not tested TDMA fREF = 19.44MHz, TCXO, fCOMP = 240kHz indicative, not tested - - - - -90 -83 -85 -77 - - - - dBc/Hz dBc/Hz dBc/Hz dBc/Hz
L(f)
Lock detect output signal (in push/pull mode) VOL VOH NOTES: V SET bias current for charge pumps 1. I SET + R
SET
LOW level output voltage HIGH level output voltage
Isink = 2 mA Isource = -2 mA
- VDD-0.4
- -
0.4 -
V V
2. The relative output current variation is defined as: DI OUT (I 2 * I 1) +2 ; with I 1 @ V 1 + 0.6 V, I 2 @ V 2 + V DDCP -0.7 V (See Figure 5.) |I 2 ) I 1| I OUT
CURRENT
IZOUT
I2
I1
VOLTAGE V1 V2
VPH
I2
I1
SR00602
Figure 5. Relative Output Current Variation
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
1.0 FUNCTIONAL DESCRIPTION 1.1 Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first divider stage. For single ended operation, the signal should be fed to one of the inputs while the other one is AC grounded. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from -18 dBm to 0 dBm, and at frequencies as high as 2.5 GHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 512 to 65535. The fractional modulus is selected by programming FMOD in the A word. There are 2 modulus to select from: when FMOD = 0, modulo 8 is selected; when FMOD = 1, modulo 5 is selected. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented by the value of NF. The accumulator works with modulo set by FMOD. When the accumulator overflows, the overall division ratio N will be increased by 1, to N + 1. The average division ratio over modulo main divider cycles (either 5 or 8) will be Nfrac + N ) NF f MOD
1.2 Auxiliary divider
The AUXin input drives a pre-amplifier to provide the clock to the first divider stage. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from -15 dBm to 0 dBm (112 to 632 mVpp), and at frequencies as high as 550 MHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 128 to 16383.
1.3 Reference divider
The reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. The 3 bit SM (SA) register (see Figure 6) determines which one of the 5 output pulses are selected as the main (auxiliary) phase detector input, thus allowing the main PFD and auxiliary PFD to operate at different frequencies.
1.4 Phase detector (see Figure 7)
The reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. The pump current is set by an external resistor in conjunction with control bits CP0 and CP1 in the C-word (see Table 1). The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps ON for a minimum time () at every cycle (backlash time) providing improved linearity.
The output of the main divider will be modulated with a fractional phase ripple. The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. Thus, fVCO = fcomp * N ) NF f MOD .
The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance.
SM="000" SM="001" SM="010" SM="011" SM="100" REFERENCE INPUT TO MAIN PHASE DETECTOR
DIVIDE BY R
/2
/2
/2
/2
SA="100" SA="011" SA="010" SA="001" SA="000"
TO AUXILIARY PHASE DETECTOR
SR01415
Figure 6. Reference Divider
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
VCC
"1" D fREF REF DIVIDER R CLK R Q
P
P-TYPE CHARGE PUMP
"1" AUX/MAIN DIVIDER X D CLK Q N R
IPH
N-TYPE CHARGE PUMP
GND
fREF
R
X
P
N
IPH
SR01451
Figure 7. Phase Detector Structure with Timing
2001 Aug 21
9
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
1.5 Main Output Charge Pumps and Fractional Compensation Currents (see Figure 8)
The main charge pumps on pins PHP and PHI are driven by the main phase detector and the charge pump current values are determined by the current at pin RSET in conjunction with bits CP0, CP1 in the C-word (see Table 1). The main charge pumps will enter speed up mode after the A-word is set and strobe goes High. When strobe goes Low, charge pump will exit speed up mode. The fractional compensation is derived from the current at RSET, the contents of the fractional accumulator (FRD) and by the program value of the FDAC. The timing for the fractional compensation is derived from the main divider.
The compensation is done by sourcing a small current, ICOMP, see Figure 9, that is proportional to the fractional error phase. For proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. The width of the fractional compensation pulse is fixed to 128 VCO cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by FDAC values (bits FC7-0 in the B-word). The fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, RSET, programming or speed-up operation. For a given charge pump, ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD FRD is the fractional accumulator value and is automatically updated. The theoretical values for FDAC are: 128 for FMOD = 1 (modulo 5) and 80 for FMOD = 0 (modulo 8).
1.6 Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. If ICOMP is the compensation current and IPUMP is the pump current, then for each charge pump: IPUMP_TOTAL = IPUMP + ICOMP.
REFERENCE R
MAIN M DIVIDE RATIO
N
N
N+1
N
N+1
CHARGE PUMP OUTPUT 2 ACCUMULATOR VALUE (FRD) FRACTIONAL COMPENSATION CURRENT (ICOMP) 4 1 3 0
PULSE WIDTH MODULATION
mA
IPUMP-TOTAL PULSE LEVEL MODULATION GRAPHS NOT TO SCALE. NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump output.
A
SR02359
Figure 8. Waveforms for NF = 2 Modulo 5 fraction = 2/5
fRF
MAIN DIVIDER
FRACTIONAL ACCUMULATOR ICOMP IPUMP
fREF
LOOP FILTER & VCO
SR01800
Figure 9. Current Injection Concept
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
1.7 Charge Pumps
The PHP and PHI charge pumps are driven by the main phase detector, while the PHA charge pump is driven by the auxiliary phase detector. The ISET value (refer to Table 1) is determined by the external resistor attached to the RSET pin. The charge pump, by default, will automatically go into speed-up mode (which can deliver up to 15*ISET for PHP_SU, and 36*ISET for PHI), based on the strobe pulse width following the A word, to reduce switching speed for large tuning voltage steps (i.e., large frequency steps). Figure 10 shows the recommended passive loop filter configuration. Note: This charge pump architecture eliminates the need for added active switches and reduces external component count. Furthermore, the programmable charge pump gains provide some programmability to the loop filter bandwidth. The duration of speed-up mode is determined by the strobe pulse width following the A word. Recommended optimal strobe width is equal to the total loop filter capacitance charge time from state 1 to state 2. The strobe width must not exceed this charge time. The strobe width is controlled by the CPU (x number of clock cycles). In addition, charge pumps will stay in speed-up mode continuously while Tspu = 1 (in D word). The speed-up mode can also be disabled by programming Tdis-spu = 1 (in D word).
Table 1. Main and auxiliary charge pump currents
CP1 0 0 1 1 CP0 0 1 0 1 IPHA 1.5xlSET 0.5xlSET 1.5xlSET 0.5xlSET IPHP 3xISET 1xlSET 3xlSET 1xlSET IPHP-SU 15xlSET 5xlSET 15xlSET 5xlSET IPHI 36xlSET 12xlSET 0 0
NOTES: 1. ISET = VSET/RSET: bias current for charge pumps. 2. CP1 is used to disable the PHI pump, IPHP-SU is the total current at pin PHP during speed up condition.
1.8 Lock Detect
The output LOCK maintains a logic `1' when the auxiliary phase detector (AND/ORed) with the main phase detector indicates a lock condition. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 period of the frequency at the input REFin+, -. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic `0') is indicated when both counters are powered down.
1.9 Power-down mode
R2 PHP[PHP-SU] R1 PHI C1 C2 C3 VCO
The power-down signal can be either hardware (PON) or software (PD). The PON signal is exclusively ORed with the PD bits in B-word. If PON = 0, then the part is powered up when PD = 1. PON can be used to invert the polarity of the software bit PD. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
SR02356
Figure 10. Typical passive 3-pole loop filter
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
2.0 SERIAL PROGRAMMING BUS
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter divide ratios, fractional compensation DAC, selection and enable bits. The programming data is structured into 24 bit words; each word includes 2 or 3 address bits. Figure 11 shows the timing diagram of the serial input. When the STROBE goes active HIGH, the clock is disabled and the data in the shift register remains unchanged. Depending on the address bits, the data is latched into the selected working registers or temporary registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A, in that order. A typical programming sequence is illustrated in Figure 12. Table 2 shows the format and the contents of each word. The D word is used for testing purposes and should be initially set to 0 for normal operation. When sending the B-word, data bits FC7-0 for the fractional compensation DAC are not loaded immediately. Instead they are stored in temporary registers. Only when the A-word is loaded, these temporary registers are loaded together with the main divider ratio.
2.1 Serial bus timing characteristics (see Figure 11)
VDD = VDDCP =+3.0 V; Tamb = +25 C unless otherwise specified. SYMBOL Serial programming clock; CLK tr tf Tcy Input rise time Input fall time Clock period - - 100 10 10 - 40 40 - ns ns ns PARAMETER MIN. TYP. MAX. UNIT
Enable programming; STROBE tSTART tW tSU;E Delay to rising clock edge Minimum inactive pulse width Enable set-up time to next clock edge 40 1/fCOMP 20 - - - - - - ns ns ns
Register serial input data; DATA tSU;DAT tHD;DAT Input data to clock set-up time Input data to clock hold time 20 20 - - - - ns ns
Application information
tSU;DAT Tcy tHD;DAT tf tr tSU;E
CLK 0 LSB MSB ADDRESS
DATA
STROBE tw tSTART
SR01417
Figure 11. Serial Bus Timing Diagram
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
POWER-ON
PROGRAM D WORD - SET DEFAULT
PROGRAM C WORD - SELECT SA, SM - SET CHARGE PUMP GAIN - SET AUX DIVIDER
PROGRAM B WORD - SELECT FDAC - SET POWER-UP OPTION - SET LOCK DETECT - SET REF DIVIDER
PROGRAM A WORD - SELECT MAIN DIVIDER - SET FRACTIONAL-N - SET FMOD
READY TO OPERATE
PROGRAM A WORD
Y
CHANGE MAIN FREQUENCY N
CHANGE FDAC N
Y
PROGRAM C WORD
Y
CHANGE AUX FREQUENCY N
PROGRAM B WORD
Y
POWER DOWN N
PROGRAM B WORD
Y
POWER UP
N POWER OFF
SR02360
Figure 12. Typical programming sequence
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
Data format Table 2. Format of programmed data
Last In p23 p22 MSB p21 p20 Serial Programming Format ../.. ../.. p1 First In LSB p0
Table 3. A word, length 24 bits
Last In Address
0 0
MSB fmod
fmod 0
LSB
N14 0 N13 1 N12 0 N11 0 N10 0 N9 1 N8 0 N7 0 N6 0 N5 1 N4 1 N3 0 N2 0 N1 0 N0 0
First In Spare
SK1 0 SK2 0
Fractional-N
NF2 0 NF1 1 NF0 0
Main Divider ratio
N15 0
Default
A word address Fractional Modulus select Fractional-N Increment N-Divider Spare
Fixed to 00. fmod = 0 is modulo 8; fmod = 1 is modulo 5. Fractional-N Increment values 000 to 111 (0 to 7). NF is a 3-bit word. N0..N15, Main divider values 512 to 65535 allowed for divider ratio. SK1, SK2 must be set to 0.
Table 4. B word, length 24 bits
Address
0 1 R9 0 R8 0 R7 0
Reference Divider
R6 1 R5 0 R4 1 R3 0 R2 0 R1 0 R0 1
Lock
L1 0 L0 0 Main 1
PD
Aux 1 0
FDAC (Fractional Compensation DAC)
FC7 FC6 1 FC5 0 FC4 1 FC3 0 FC2 0 FC1 0 FC0 0
Default REF-Divider
B word address Lock detect output
Fixed to 01 R0..R9, Reference divider values 4 to 1023 allowed for divider ratio. R <9:0>. L1 L0 0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull). 0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain). 1 0 Main lock detect signal present at the LOCK pin (push/pull). 1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull). When auxiliary loop and main loop are in power down mode, the lock indicator is low. PON pin is tied to GND PON pin is tied to VDD Main = 1: power-on to Main PLL. Main = 0: power-down to Main PLL. Aux = 1: power-on to Aux PLL. Aux = 0: power-down to Aux PLL. Main = 0: power-on to Main PLL. Main = 1: power-down to Main PLL. Aux = 0: power-on to Aux PLL. Aux = 1: power-down to Aux PLL.
Power down (PD)
Fractional Compensation
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 5. C word, length 24 bits
Address
1 0 A13 0 A12 0 A11 0 A10 0 A9 0
Auxiliary Divider
A8 1 A7 1 A6 1 A5 0 A4 0 A3 1 A2 0 A1 1 A0 0 1
CP
CP1 CP0 1 SM2 0
SM
SM1 0 SM0 0 SA2 0
SA
SA1 0 SA0 0
Default A-Divider
C word address Charge pump current Ratio Main comparison select Aux comparison select
Fixed to 10 A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio. CP1, CP0: Charge pump current ratio, see Table 1. SM comparison divider select for main phase detector. SA Comparison divider select for auxiliary phase detector.
Table 6. D word, length 24 bits
Address
1 1 0 - 0 - 0 - 0 - 0 Tdis-spu 0 Tspu 0 - 0 - 0
Synthesizer Test Bits
- 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0
Default D word address Tdis-spu = 1 Tspu = 1
Fixed to 110. Speed-up mode disabled. NOTE: All other test bits must be set to 0 for normal operation. Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation.
2001 Aug 21
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Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS
3000 2000 1000 Icp (uA) 0 -1000 -2000 -3000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 81 A ISET = 164 A ISET = 204 A
ISET = 164 A ISET = 81 A Icp (uA)
2000 1000 0 -1000 -2000 -3000 0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE(V)
COMPLIANCE VOLTAGE (V)
SR02331
SR02332
Figure 13. PHI Charge Pump Output vs. ISET (CP = 01_12x; Temp = 25 _C)
Figure 14. PHI Charge Pump Output vs. Temperature (CP = 01_12x; VDD = 3.0 V; ISET = 164 mA)
8000 6000 4000 Icp (uA) Icp (uA) 2000 0 -2000 -4000 -6000 -8000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 164 A ISET = 204 A ISET = 81 A ISET = 81 A ISET = 204 A ISET = 164 A
8000
4000 2000 0 -2000 -4000 -6000 -8000
COMPLIANCE VOLTAGE (V)
SR02333
Figure 15. PHI Charge Pump Output vs. ISET (CP = 00_36x; Temp = 25 _C)
Figure 16. PHI Charge Pump Output vs. Temperature (CP = 00_36x; VDD = 3.0 V; ISET = 164 mA)
800 600 400 Icp (uA) 200 0 -200 -400 -600 -800 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 81 A ISET = 164 A ISET = 204 A Icp (uA) ISET = 204 A ISET = 164 A ISET = 81 A
800
400 200 0 -200 -400 -600 -800
COMPLIANCE VOLTAGE
SR02335
Figure 17. PHP Charge Pump Output vs. ISET (CP = 10_3x; VDD = 3.0 V; Temp = 25_C)
Figure 18. PHP Charge Pump Output vs. Temperature (CP = 10_3x; VDD = 3.0 V; ISET = 164 mA)
2001 Aug 21
15
I I I I I I IIIIIIIIIII I IIIIIIIIIII I II III II IIIIIIIII II II II II II II IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIII II III III I II I I II
600
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE (V)
SR02336
3.00
II II I I I I II IIII II IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII I I I II I I I IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIII IIIII I II II II
6000
-40 C +25 C +85 C
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE (V)
SR02334
-40 C +25 C +85 C
3.00
3.00
II II II II I I I II II IIIIII II I IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII I II I I I I I I IIIIIIIIIIII III IIIIIII IIIIIIIIIII IIIIIIIIIII II
-40 C +25 C +85 C
ISET = 204 A
3000
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
250 200 150 100 Icp (uA) 50 0 -50 -100 -150 -200 -250 0.00 ISET = 164 A ISET = 204 A 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 81 A Icp (uA)
150 ISET = 81 A 100
50
0
-50 -100 -150 -200 -250
COMPLIANCE VOLTAGE (V)
SR02337
Figure 19. PHP Charge Pump Output vs. ISET (CP = 11_1x; VDD = 3.0 V; Temp = 25 _C)
Figure 20. PHP Charge Pump Output vs. Temperature (CP = 11_1x; VDD = 3.0 V; ISET = 164 mA)
1500 1000 500 Icp (uA) 0 ISET = 81 A -500 -1000 -1500 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 164 A ISET = 204 A ISET = 204 A ISET = 164 A
1500
500 Icp (uA) ISET = 81 A 0 -500 -1000 -1500
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02339
SR02340
Figure 21. PHP-SU Charge Pump Output vs. ISET (CP = 01_5x; VDD = 3.0 V; Temp = 25 _C)
Figure 22. PHP-SU Charge Pump Output vs. Temperature (CP = 01_5x; VDD = 3.0 V; ISET = 164 mA)
4000 3000 2000 Icp (uA) 1000 0 -1000 -2000 -3000 -4000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 81 A ISET = 164 A ISET = 204 A ISET = 204 A ISET = 164 A Icp (uA) ISET = 81 A
4000 3000 2000 1000 0 -1000 -2000 -3000 -4000
-40 C +25 C +85 C
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02341
SR02342
Figure 23. PHP-SU Charge Pump Output vs. ISET (CP = 00_15x; VDD = 3.0 V; Temp = 25 _C)
Figure 24. PHP-SU Charge Pump Output vs. Temperature (CP = 00_15x; VDD = 3.0 V; ISET = 164 mA)
2001 Aug 21
16
3.00
3.00
I I II I I II II II IIIII IIII IIIIIIIIII IIIIIIIIIII IIIIIIIIIII I I II I I I IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIII IIIII II II II
1000
II II II II II I II II I I IIIIIIII I IIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII I I I II I I I II IIII III IIII III I II II I IIIIIIIIIIII IIIIIIIIIIIII II IIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIII II
-40 C +25 C +85 C 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 COMPLIANCE VOLTAGE (V)
ISET = 204 A ISET = 164 A
250 200
SR02338
-40 C +25 C +85 C
3.00
I I I I I I I I I IIIIIIIIIII III I IIIIIIIII IIIIIIIII IIIIIIIIII II II II IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII II I IIII IIIIIIIIII I I I I II II II
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
150 100 50 Icp (uA) 0 ISET = 81 A -50 ISET = 164 A -100 -150 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 204 A Icp (uA) ISET = 81 A ISET = 204 A 100 50 -100
0
-50 -100 -150
COMPLIANCE VOLTAGE (V)
SR02343
Figure 25. PHA Charge Pump Output vs. ISET (CP = 11_0.5x; Temp = 25 _C)
400 300 200 100 Icp (uA) 0 -100 -200 -300 -400 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ISET = 81 A ISET = 164 A ISET = 204 A ISET = 204 A ISET = 164 A ISET = 81 A
Figure 26. PHA Charge Pump Output vs. Temperature (CP = 11_0.5x; VDD = 3.0 V; ISET = 164 mA)
400
200 100 Icp (uA) 0
-100 -200 -300 -400
COMPLIANCE VOLTAGE (V)
SR02346
Figure 27. PHA Charge Pump Output vs. ISET (CP = 10_1.5x; VDD = 3.0 V; Temp = 25 _C)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 -51
Figure 28. PHA Charge Pump Output vs. Temperature (CP = 10_1.5x; VDD = 3.0 V; ISET = 164 mA)
MINIMUM SIGNAL INPUT LEVEL (dBm)
2.6V 3.0V 3.6V MINIMUM SIGNAL INPUT LEVEL (dBm)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 -51
INPUT FREQUENCY (MHz)
SR02347
Figure 29. Main Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25 _C; ISET = 164 A; NF = 0; MOD = 8; N = 853)
Figure 30. Main Divider Input Sensitivity vs. Frequency and Temperature (ISET = 164 A; NF = 0; MOD = 8; N = 853; VDD = 3.0 V)
2001 Aug 21
17
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 INPUT FREQUENCY (MHz)
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
I II IIIIIIIIIII IIIIIIIIIIII III I I III IIIIIII IIIIIIIIIII II II II II I II I I I II IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIII IIIII I IIII I I I I
300
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
COMPLIANCE VOLTAGE (V)
SR02345
-40 C +25 C +85 C
SR02348
3.00
II IIIIIIIIIIII II II I I I IIIIII I I IIIIIIIIIII IIIIIIIIIII II II II II I I IIIIIIIIIIIII I IIIIIIII II IIIIIIIIIII IIIIIIIIIII I II II I I I I
-40 C +25 C +85 C 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 COMPLIANCE VOLTAGE (V)
ISET = 164 A
SR02344
-40 C +25 C +85 C
3.00
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0 -3 MINIMUM SIGNAL INPUT LEVEL (dBm) -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 2.6V 3.0V 3.6V MIMINUM SIGNAL INPUT LEVEL (dBm) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 50 55 60 900 950 -40 C +25 C +85 C
FREQUENCY (MHz)
SR02349
FREQUENCY (MHz)
SR02350
Figure 31. Auxiliary Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25 _C; ISET = 164 A; Divider Ratio = 213)
Figure 32. Auxiliary Divider Input Sensitivity vs. Frequency and Temperature (ISET = 164 A; Divider Ratio = 213; VDD = 3.0 V)
MINIMUM SIGNAL INPUT LEVEL (dBm)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 2.6V 3.0V 3.6V
MINIMUM SIGNAL INPUT LEVEL (dBm)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 0 5 10 15 20 25 30 35 40 45 65 70 FREQUENCY (MHz) -40 C +25 C +85 C
FREQUENCY (MHz)
SR02351
SR02352
Figure 33. Reference Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25 _C; ISET = 164 A; Divider Ratio = 682)
9.00
Figure 34. Reference Divider Input Sensitivity vs. Frequency and Temperature (ISET = 164 A; Divider Ratio = 682; VDD = 3.0 V)
8.50 TOTAL CURRENT (mA)
8.00
7.50
7.00 -40 C +25 C +85 C
6.50
6.00 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 SUPPLY VOLTAGE (V)
SR02353
Figure 35. Total Supply Current vs. Temperature (ISET = 164 A)
2001 Aug 21
18
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
2001 Aug 21
19
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm
SOT564-1
2001 Aug 21
20
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
NOTES
2001 Aug 21
21
Philips Semiconductors
Product data
2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
SA8027
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 09-01
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 08745
Philips Semiconductors
2001 Aug 21 22

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